The present invention is related to Field Programmable Gate Array (FPGA) integrated circuits and, more particularly, to floating gate MOS transistors used as switching elements in an FPGA.
An FPGA requires some means to programmably interconnect the FPGA. Typically, an antifuse, such as described in U.S. Pat. No. 5,015,885, which issued to A. El Gamal and S. S. Chiang on May 14, 1991, or an N-channel MOS transistor, is used as the programmable switching element used to interconnect wiring and the circuit elements of the FPGA. When an MOS transistor is used as the programmable switching element, it must be controlled by the memory bit of a programmable storage element. Most commonly, the storage element is a static RAM cell, (e.g., see U.S. Pat. No. 4,870,302, which issued to R. H. Freeman on Sep. 26, 1989). However, other storage elements can be used. For example, a patent application, U.S. Ser. No. 08/032,610, filed Mar. 17, 1993 by Richard D. Freeman, describes the use of a dynamic RAM cell as the storage element.
While combining the functions of the switching and storage elements, an antifuse switching element has the disadvantage that the antifuse is not reprogrammable. This single time programmability makes the antifuse difficult to test and unsuitable for a large class of applications where reprogrammability is required. RAM-based FPGAs are reprogrammable, but the programming is lost whenever power is turned off. A separate storage memory must be used to store the programmed pattern and the FPGA must be reprogrammed every time it is powered up. Furthermore, switching based on volatile RAM, such as static RAM and dynamic RAM cell elements, tend to occupy a large amount of space in the integrated circuit since the switch cannot be closely integrated with the memory cell.
Another type of memory cell, that of the non-volatile, reprogrammable transistor memory (NVM), have been available. NVM cells are MOS transistors with floating gates which may be charged and/or discharged by either channel hot electron (CHE) programming or Flower-Nordheim (FN) tunneling. Charging and/or discharging the floating gate provides for the non-volatile programmability features of these NVM technologies. NVM technologies have been widely used for memory and also for programmable logic devices (PLDs), where the programming and logic functions are integrated into a single cell structure. PLDs are simpler logic arrays than FPGAs with a very ordered memory-like interconnection structure, implementing programmable logic array (PLA) structures directly. On the other hand, FPGAs are typically used to implement random logic functions, a much more complex task.
The floating gate structure of these NVM cells is sensitive to hot electron injection. In fact, hot electron injection is the basis of CHE technology. One reason that NVM cells have not been used as general purpose switching elements is that the voltage across the source-drain terminals of the floating gate MOS transistor must be carefully controlled during operation to prevent inadvertent self-programming of the NVM cell by hot electron injection into the floating gate. NVM cells self-program themselves during operation if a large voltage is applied between the source and drain of the transistor while the transistors are "on". This voltage restriction has limited the use of NVM technology to memory and memory-like structure, e.g., those found in PLA or PAL logic devices, which can be addressed with a small fixed voltage and sensed with a sense amplifier.
In these devices, self-programming has been prevented by carefully biasing the NVM transistor to a "safe" condition, i.e., a state where no hot electrons are generated, during its operating, or "read" state. "Read" operation is commonly performed by clamping a small fixed voltage (e.g., 1 V) to the drain of the NVM transistor to be selected, then selecting the NVM transistor by capacitively coupling a bias voltage into its floating gate, and measuring the current through the device with a sense amplifier to determine whether the current through the transistor is above a predetermined minimum. The clamping voltage applied to the selected NVM transistor during this "read" operation limits the maximum voltage which appears across the source-drain terminals of the transistor to prevent hot electron generation.
Heretofore, it has not been believed practical to apply NVM technology to general purpose switching of full voltage signals, i.e., where the voltage to be switched is larger than the maximum voltage permitted across the source-drain terminals of the NVM transistor to avoid the possibility of inadvertent self-programming of the transistor), due to the restriction on the voltage across the source/drain terminals of an "on" NVM transistor. Without this voltage restriction, hot electrons are generated which are attracted to the floating gate and which discharge the positive voltage on the gate of the device. The NVM transistor is deprogrammed. Thus over the past 20 years since their inception in memory devices, NVM transistors have not been used as general purpose switching elements.
The present invention solves or substantially mitigates the problem of hot electron generation and the subsequent hot electron injection into the floating gate of an NVM transistor which is used to switch a full voltage signal. This permits the NVM transistor to be used as a switching element in an FPGA.